1. Technical Field of the Invention
The present invention relates to a storing method for a non-volatile memory cell array with error correction code (such as a code used for identifying and correcting, in the reading step, a possible faulty cell containing a wrong stored datum).
The present invention also relates to a memory electronic device comprising non-volatile memory cells organized with a plurality of arrays of N memory cells, which is able to store data or information as a group of bits, each array being associated with an error correction code to identify and recover a possible faulty cell containing wrong bits.
The invention particularly, but not exclusively, relates to a memory device of the Flash type and the following description is made with reference to this field of application by way of illustration only.
2. Description of Related Art
As is well known, memory electronic devices with non-volatile memory cells of the Flash type are widely used to store a huge amount of information in a compact support, with high capacity and reliability.
Non-volatile memory electronic devices are devices integrated on a semiconductor substrate comprising a plurality of cells normally organized in a matrix, comprising a plurality of sectors each with rows and columns of cells.
The cells of Flash memories can be of the two-level type, and in this case the values stored can be two, corresponding to a logic value 0 and to a logic value 1 which, from the electric point of view, make reference to a value of the threshold voltage Vth. The amount of information being stored in such a functional context is equal to one bit per cell.
Alternatively, Flash memory cells can be of the multilevel type, which results, from the electric point of view, in a number of possible values of the threshold voltage higher than one, and their value depends on the number of bits being stored in the same cell. The amount of information which can be stored in a single multilevel cell is much increased over that which can be stored a two-level type cell.
To better understand the aspects of the present invention it is important to understand how the programming steps occur in multilevel Flash cells.
The writing operation of a Flash cell consists in varying the threshold voltage thereof by the desired amount, and storing electrons in the floating gate region.
To program the cell while obtaining threshold voltage distributions with a precision being sufficient for the realization of multiple levels, the voltage applied onto the control gate terminal can be variable with step-like increases starting from a minimum value to the attainment of a maximum value. The width of the voltage step, being the gate terminal under optimal conditions, is equal to the threshold jump which is to be obtained.
The use of a step-like gate voltage raises a timing problem to efficiently bring the programming step to an end. To minimize the duration of the programming times it is convenient to program a high number of cells in parallel.
The programming in parallel can occur by using an algorithm called “program & verify”, in the course of whose execution each programming pulse is followed by a reading step of the cells, during the programming, to determine if they have reached the threshold value or not.
If a given cell has been correctly programmed, it will no longer receive any programming pulse, while the cells which have not reached a desired threshold yet will be reprogrammed by the same algorithm. To this aim some programming circuits are used which allow one to selectively apply, onto the drain terminals of the cells to be programmed, predetermined values of programming voltages.
In the meantime, also the voltage to be applied onto the source terminal is to be kept under control with great accuracy, both during the programming step and during the reading step.
For multilevel cells, the accurate control of the distributions of the cell thresholds becomes fundamental so that these are correctly positioned below the programmed threshold voltage values Vth for the written cells and below the erase verify potential for the erased cells.
Flash memory cells have a great capacity of maintaining the datum stored. However, on the order of some cells out of a million cells, there exist cells, called anomalous or faulty cells, which have a capacity of keeping or preserving the stored datum for much less time than that of the so called “typical” cell.
The presence of the anomalous cells in memory devices is a source of criticality during the storage and/or the reading of the data inserted and, naturally, in multilevel devices such criticality, induced by the anomalous cells, increases.
To maintain a high reliability level in Flash memory electronic devices the use of a storing method is known comprising an error correction code (ECC) which is a code generated during the storage so as to protect against an error present in the stored bits.
In reading, this error correction code (ECC) allows one to identify and to correct a datum read by a faulty cell positioned inside an array of N cells.
The code (ECC) of the known type has proved to be efficient in increasing the reliability of a memory electronic device. However, its use has a remarkable limitation.
It is known, in fact, that a common operation on the memory electronic devices is re-storage or bit manipulation. This is an operation which allows the storage transition of one or more cells of an array (such as the passage of the logic value of a cell from “0” to “1”), but which does not allow the contrary transition (such as to erase the cell to “0”).
The re-storage operation or bit manipulation, is generally requested in software implementing a flash file system, i.e., in the algorithms implementing a file system.
Further to the re-storage operation, a new code (ECC) is redefined or recalculated but it is not certain that the new error correction code has, with respect to the old one, the re-storage transitions 1→0. In practice the new error correction code (ECC) redefined does not ensure that the code itself can be stored, since there exists a high probability that the transition 0→1 is required and the cells where the re-storage or bit manipulation has been carried out are covered.
A solution to this problem, already applied in some types of Flash memory electronic devices, for example those of the NAND type, has overcome the problem by prearranging a suitable writing area for the code (ECC) having dimensions equal to a multiple with respect to a minimum necessary area. Thus, during the re-storage, the code (ECC) can be updated or refreshed for some times and be re-written in different points. For example each N bytes, usually equal to 512, M are allocated, typically 16 additional bytes, accessible with dedicated commands, for the management of the ECC or error correction, independently from the fact that there exists an effective need of refreshing the memory content.
The re-written code (ECC) ensures the covering of the re-programmed areas.
Although advantageous under several aspects and substantially meeting the aim, the solution proposed shows however some drawbacks.
In fact, the solution is devoid of universality since it cannot be applied to all the typologies of Flash non-volatile memory devices.
For example, the solution cannot be applied to the devices of the “execute in place” type where the high requests for performances in reading require that the possible error correction occurs with a very small delay, in the order of a few nanoseconds.
In fact, the application of this solution in an “execute in place” device would involve that the reading of the data stored in an array of N cells and in the code (ECC) occurs simultaneously and that the possible error of a bit in one of the N cells of the array is instantaneously corrected.
Moreover, the solution proposed needs to read, in a serial way, all the codes (ECC), generated further to a bit manipulation and stored in the writing area arranged, until the valid one to be applied in the reading step for the correction is found. This naturally implies a remarkable increase of the access time for the device which penalizes its performances.
The technical problem underlying the present invention is that of devising a storing method for an array of N cells of a non-volatile memory device provided with code (ECC), the method having such functional characteristics as to allow to make the code (ECC) reliable and usable further to re-storage or bit manipulation of the array of N cells.
Another aim of the invention is that of providing a method which can be universally applied to all the non-volatile memory devices.
A further aim of the present invention is that of devising a device comprising a plurality of arrays of N cells of non-volatile memories with an error correction code (ECC), this code being quickly accessible and identifiable, avoiding the penalization of the access time and maintaining, in the meantime, the device performances high, as well as of avoiding the increase of the area intended for the storage of the memory cells overcoming the limits and the drawbacks of the solutions proposed by the prior art.